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Papers: on the plane to SPLASH 2014

Another conference, another plane ride, another blog post.

Academic urban legends (Ole Bjørn Rekdal; full text)

Is spinach a good source of iron? Turns out it isn’t, despite widespread belief to the contrary (go ahead, tell your parents). This article describes how the academic explanation for this widespread belief evolved through a game of citation telephone. (I won’t spoil any more of the story here – you’ll have to read the article.)

Data Size Optimizations for Java Programs (Ananian, Rinard; PDF, gratis PDF)

From the contributions section: {% blockquote %} Implementation: We have fully implemented all of the analyses and techniques presented in the paper. Our experience with this implementation enables us to discuss the pragmatic details necessary for an effective implementation of our techniques. {% endblockquote %} It’s not “just engineering”.

Computational Sprinting (Raghavan, Luo, Chandawalla, Papaefthymiou, Pipe, Wenisch, Martin; PDF, gratis PDF; Raghavan, Emuerian, Shao, Papaefthymiou, Pipe, Wenisch, Martin; PDF, gratis PDF)

Intel’s Turbo Boost can increase voltage and clock speed of one core of a multicore processor when the other cores are idle, effectively reallocating the TDP of those cores. Computational sprinting is the obvious inverse: run normally with one core, but turn on more cores in short, thermally-unsustainable sprints. Often these “cores” are uncore parts or integrated accelerators. These papers explore the design space of computational sprinting in the context of smartphones, which are constrained by all of energy, thermal dissipation, volume and weight. We usually assume chips are packaged to maximize the rate of thermal dissipation, but computational sprinting additionally requires thermal capacitance to store the heat generated by a sprint for later dissipation during nominal operation.

Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multiprocessors (Raghunathan Turakhia, Garg, Marculescu; PDF, gratis PDF)

When designing a chip that cannot power all its components simutaneously (i.e., it must leave some “dark silicon”), the obvious approach is to include a small number of general-purpose processors plus many different accelerators, aiming to use the parts of the chip most efficient for a particular workload. This paper argues we should instead build homogeneous chips with many general-purpose processors; due to variations in manufacturing, some processors will support higher clock rates or will use less power than the others, and we can “cherry-pick” the best ones. Under a model in which a parallel task’s runtime is dominated by the slowest processor, having more general-purpose processors to pick from results in a less-slow processor being the long pole, with a corresponding decrease in execution time. A similar analysis holds for power because power grows with the square of voltage, so the processor requiring the highest voltage for reliable operation has a disproportionate impact on the total power.